This invention relates to timing generators which generate test pulses used for testing of semiconductor storage devices.
The timing generators generate test pulses at predetermined timings. Herein, groups of test pulses are sequentially generated by predetermined intervals of time, so they are repeated by predetermined cycles. In some cases, the timing generators are requested to generate test pulses in such a way that generation of test pulses is started at different timing with respect to each of the cycles.
FIG. 7 is a block diagram showing an example of the timing generator which repeatedly generates test pulses. This example of the timing generator is designed to start generation of 2 test pulses at a different timing with respect to each of test cycles, wherein the 2 test pulses are disposed in time with a certain interval of time.
A central processing unit (i.e., CPU) 118 has 4 lines, i.e., a data line DOUT of m bits provided for read/write operations of data, an address line ADR of n bits and write enable lines WE1, WE2. Herein, the data line DOUT is used to access random-access memories (i.e., RAMs) 109-1 and 109-2. Incidentally, the address line ADR is designed as a 4-bit address line, for example.
FIGS. 8A and 8B are time charts showing waveshapes of signals monitored at several portions of the timing generator of FIG. 7. There are provided 6 test cycles, denoted by `A` to `F`, which are used to write timing data to the RAMs 109-1 and 109-2. That is, the CPU 118 transfers different data on to the data line DOUT, address line ADR and write enable lines WE1, WE2 respectively with respect to each of the test cycles. Incidentally, data DOUT, outputted from the CPU 118, corresponds to timing data; and it is represented by a certain number in decimal notation.
In the test cycle A shown in FIG. 8A, the CPU 118 transfers `0` as an address ADR; it also transfers `0` as data DOUT. Herein, a selector 108 selects the address ADR outputted from the CPU 118. In addition, the CPU 118 outputs a write pulse WE1 onto the write enable line WE1 so that the RAM 109-1 is placed in a write enable state. Therefore, in the test cycle A, data `0` (i.e., timing data represented by a decimal number `0`) is written into an address ADR0 of the RAM 109-1.
In the test cycles B and C, the CPU 118 operates similarly to the aforementioned test cycle A. Namely, in the test cycle B, data `10` is written into an address ADR1 of the RAM 109-1. In the test cycle C, data `20` is written into an address ADR2 of the RAM 109-1.
Next, in the test cycle D shown in FIG. 8B, the CPU 118 transfers `0` as an address ADR; and it also transfers `5` as data DOUT. Even in this test cycle, the selector 108 continues to select the address ADR outputted from the CPU 118. In addition, the CPU 118 outputs a write pulse onto the write enable line WE2 so that the RAM 109-2 is placed in a write enable state.
So, in the test cycle D, data `5` is written into an address ADR0 of the RAM 109-2. Similarly, in the test cycle E, data `15` is written into an address ADR1 of the RAM 109-2. In the test cycle F, data `25` is written into an address ADR2 of the RAM 109-2.
As described above, multiple timing data are written into the RAMs 109-1 and 109-2 respectively. Actually, certain timing data are written into all addresses of the RAMs 109-1 and 109-2. For convenience' sake, the description regarding write operations is given with respect to a limited number of test cycles, i.e., A to F; hence, the description regarding write operations of other test cycles is omitted.
FIG. 9A shows a memory map for storing the timing data in the RAM 109-1, whilst FIG. 9B shows a memory map for storing the timing data in the RAM 109-2.
Incidentally, a decimal number representing each timing data shows an elapsing time, using the unit of nano second(s) (abbreviated by `ns`), which elapses from a reference time which is set in advance.
FIG. 10 is a time chart showing test cycles G to I which are used to read the timing data from the RAM 109-1 and 109-2.
Now, a reference clock signal T0 is input to a clock terminal 107 shown in FIG. 7. In the test cycle G, a clock pulse of the reference clock signal T0 is input to the clock terminal 107, so that a pattern generator 106, configured by a counter circuit, outputs the address ADR0. Herein, the selector 108 selects an output of the pattern generator 106. So, the address ADR0 is delivered to an address input ADR of the RAM 109-1 and an address input ADR of the RAM 109-2.
In the test cycle G, the CPU 118 outputs different data onto the data line DOUT, so data `0` is supplied to the RAM 109-1 whilst data `5` is supplied to the RAM 109-2. Herein, an output `DOUT` of the RAM 109-1 is forwarded to a pulse generator 110-1, whilst an output `DOUT` of the RAM 109-2 is forwarded to a pulse generator 110-2.
The aforementioned reference clock signal T0 is input to a delay line (or delay circuit) 111, wherein it is delayed by a certain delay time td whose value is know in advance. So, the delay line 111 outputs a trigger signal T0', which is delivered to the pulse generators 110-1 and 110-2 respectively. The trigger signal T0' consists of trigger pulses which delays from the clock pulses of the reference clock signal T0 by the delay time td.
So, the pulse generator 110-1 outputs a pulse of a pulse signal P1 after the elapsing time, which is set by the aforementioned timing data given from the RAM 109-1, elapses from a timing to input a trigger pulse of the trigger signal T0'. Similarly, the pulse generator 110-2 outputs a pulse of a pulse signal P2 after the elapsing time, which is set by the timing data given from the RAM 109-2, elapses from a timing to input a trigger pulse of the trigger signal T0'.
The aforementioned pulse signals P1 and P2 are subjected to logical sum (or OR operation) by an OR gate 114. So, the OR gate 114 provides an output pulse signal P0 at an output terminal 117.
In the test cycle G, the timing data given from the RAM 109-1 represents a decimal number `0`, whilst the timing data given from the RAM 109-2 represents a decimal number `5`. So, in the test cycle G, a first output pulse appears at the output terminal 117 when the time `td` elapses from the input timing of the clock pulse of the reference clock signal T0; and a second pulse appears when a time `td+5ns` elapses after the input timing of the clock pulse.
In the next test cycle H, when a clock pulse of the reference clock signal T0 is input to the timing generator of FIG. 7, an address ADR1 outputted from the pattern generator 106 is delivered to the RAMs 109-1 and 109-2 via the selector 108.
On the basis of the address ADR1, an output DOUT of the RAM 109-1 corresponds to data `10` (see FIG. 9A), whilst an output DOUT of the RAM 109-2 corresponds to data `15` (see FIG. 9B). Thus, 2 pulses sequentially appear on the output pulse signal P0 of the output terminal 117 after an input timing of the clock pulse in the test cycle H. That is, a first pulse appears when a time `td+10ns` elapses after the input timing of the clock pulse; then, a second pulse appears when a time `td+1ns` elapses after the input timing of the clock pulse.
The aforementioned operations are repeated with respect to the other test cycles (e.g., test cycle I); hence, the description thereof will be omitted.
In short, the test cycles which starts from the test cycle G are used to provide 2 pulses (called `test pulses`) respectively. Herein, generation of the 2 test pulses differs in timing with respect to each test cycle, wherein a certain duration is maintained between the 2 test pulses, regardless of the test cycles.
The aforementioned example of the timing generator shown in FIG. 7 is designed to provide 2 test pulses with respect to each test cycle. For this reason, the timing generator requires 2 sets of the RAMs and pulse generators, wherein each of the RAMs is provided to store timing data whilst each of the pulse generators is provided to generate a single test pulse based on timing data with respect to each test cycle.
In general, the pulse generator has a complicated configuration which contains multiple counter circuits. This causes complication in overall circuit configuration of the timing generator as a whole. In addition, some timing generators require a large number of RAMs. In this case, the overall circuit configuration of the timing generator as a whole should be further complicated. In short, the complication in circuit configuration of the timing generator highly depends on the number of RAMs as well as the number of pulse generators. So, it is demanded to downsize the circuit configuration of the timing generator.